Skip to main content
English
Čeština
Deutsch
Español
Français
GÃ idhlig
Latviešu
Magyar
Nederlands
Português
Português do Brasil
Suomi
Log In
Email address
Password
Log in
Have you forgotten your password?
Home
Browse Our Collection
Researchers
Scholarly Output
Consultancy/Projects
Statistics
Log In
Email address
Password
Log in
Have you forgotten your password?
Home
Faculties / Institutes
Lee Kong Chian Faculty of Engineering and Science
Published Scholarly Output
Vacuum Reflow Process Optimization for Solder Void Size Reduction in Semiconductor Packaging Assembly
Details
Export
Statistics
Options
Show all metadata (technical view)
Vacuum Reflow Process Optimization for Solder Void Size Reduction in Semiconductor Packaging Assembly
Journal
IEEE Transactions on Components, Packaging and Manufacturing Technology
ISSN
2156-3950
Date Issued
2022-08
Author(s)
Siang Miang Yeo
Ho Kwang Yow
Lee Kong Chian Faculty of Engineering and Science
Keat Hoe Yeoh
Shahrul Haizal bin Ishak
DOI
10.1109/TCPMT.2022.3189995
File(s)
Loading...
Download
Name
Picture1.png
Type
personal picture
Size
3.11 KB
Format
PNG
Checksum
(MD5):21881560e0c3c9c06b18c6e8fdc11acf
