Design and analysis of 3-NM strained and conventional finfets

This paper presents a comprehensive framework that encompasses the design, characterization, and in-depth analysis of a 3-nm strained n-channel SiGe FinFET and its conventional Si counterpart. The integrity of our design is firmly established through intricate simulations that precisely replicate the transistor’s output and transfer characteristics. It is particularly noteworthy that these characteristics harmoniously align with the well-established benchmarks defining an operational MOSFET. By comparing the performance of both transistors, we reveal the distinct advantages of the strained FinFET. By employing the silicon-on-insulator (SOI) substrate configuration, the leakage currents of both FinFETs are found to be comparatively low. It is also observed that the strained tri-gate transistor delivers a more robust drive current. This phenomenon is attributed to the enhanced carrier mobility induced by the compressive strain within the silicon channel. Additionally, we lay out in detail the design specifications underpinning the architecture of the transistor. © 2006–2025 Asian Research Publishing Network (ARPN). All rights reserved.