Yee Chyan TanHarikrishnan RamiahSharifah Fatmadiana Wan Muhamad HattaNai Shyan LaiChee-Cheow LimRui P. MartinsPui-In MakYong Chen2025-07-252025-07-252025-0810.1109/TPEL.2025.3558005https://dspace-cris.utar.edu.my/handle/123456789/11265This article presents an output-capacitorless low-dropout regulator (OCL-LDO), merging with a hybrid push-pull buffer. The hybrid push-pull buffer implements a dynamic and adaptive biasing push-pull gate driving circuit, achieving stability without needing a complex compensation circuit and external load capacitor. Our devised OCL-LDO can operate with a load current range of 0-30 mA, with a quiescent current of 7 mu A at zero load current. The proposed OCL-LDO is fabricated in a 0.18-mu m CMOS process with an active area of 0.03 mm(2). Measurement results show that with a load current stepping from 0-30 mA and an edge time of 100 ns, the output voltage undershoot is 0.14 V, with a corresponding recovery time of 150 ns. The measured load regulation is 0.207 mV/mA at a supply voltage of 1.15 V and a dropout voltage of 0.15 V.enTransistorsLogic gatesCircuit stabilityCapacitorsTransient analysisTransient responseCapacitanceRegulationComplexity theoryCharge pumpsAdaptive biasinganalog low-dropout regulators (IDOs)CMOSdynamic biasingoutput-capacitorless LDO (OCL-LDO)push-pull bufferLOW-DROPOUT REGULATORVOLTAGE REGULATORSBANDWIDTHMHZMUjournal-article