VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM)

Loh Siu HongYou Hong Liew0000-0002-8754-6174Jia Jia Sim2024-10-182024-10-182022-10-21https://doi.org/10.1109/ICCSCE54767.2022.9935582https://dspace-cris.utar.edu.my/handle/123456789/3456VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM)proceedings-article