Pei Jie ChanHarikrishnan RamiahYing Yin Teo0009-0005-9827-4302Yee Chyan TanGabriel Chong2026-09-172026-09-172025-11-24979-833159455-810.1109/ICSyS65149.2025.11379907https://dspace-cris.utar.edu.my/handle/123456789/11690This paper presents a high-accuracy, supplycompensated current reference circuit operating from a 1.2-1.8 V supply in a 130 nm Complementary Metal-Oxide-Semiconductor (CMOS) process. The proposed design achieves a line sensitivity of 762.48 ppm/V and temperature coefficients (TC) of 2423.42 ppm/°C and 2290.02 ppm/°C over temperature ranges of 0°C to 70°C and -25°C to 125°C, respectively - unlike conventional current reference circuits, which are unable to compensate for both supply and temperature variations simultaneously. By implementing a self-biased current source based on a beta-multiplier circuit, the design minimizes the effect of input voltage fluctuations on the output current while maintaining power consumption below twice the reference current. The robustness of the design across supply and temperature variations is verified by the simulation results presented in this paper. © 2025 IEEE.encurrent referenceline sensitivitytemperature compensationIntegrated circuit designSensitivity analysisTiming circuitsComplementary metal oxide semiconductor processComplementary metal-oxide-semiconductor technologiesCurrent referenceCurrent reference circuitsHigh-accuracyLine sensitivityTemperature coefficientTemperature compensationTemperature rangeTemperature variationCMOS integrated circuitsMOS devicesTemperature distributionproceedings-article