Hao Wuang LeongKim Ho Yeap 葉金豪0009-0005-9827-4302Yee Chyan TanTun Zainal Azni Zulkifli2025-07-252025-07-252025-03-2410.4025/actascitechnol.v47i1.70205https://dspace-cris.utar.edu.my/handle/123456789/11264This paper presents the design of a 60 GHz low noise amplifier (LNA) compliant with the IEEE 802.11ay network standards. The proposed LNA employs SilTerra 0.13 mu m RF CMOS technology (April 2018 version) for its design and is developed based on the single-stage cascode topology. The performance of the design has been optimized using the source degeneration technique with gain-boosting and middle inductors. Due to the limitations of the process design kit (PDK), custom inductors have been developed for the LNA circuit. The inductors use ultra-thick metal (UTM) with a copper thickness of 3.3 mu m. At 60 GHz, the proposed LNA has a simulated input reflection coefficient (S-11) of-15.71 dB, reverse gain (S-12) of-15.83 dB, forward gain (S-21) of 7.25 dB, output reflection coefficient (S-22) of-8.78 dB, noise figure (NF) of 6.79 and minimum noise figure (NFmin) of 6.55 dB. It is also unconditionally stable at 60 GHz with a simulated Rollett stability factor (K) of 1.27 and B1 stability factor of 0.79. The design shows high linearity, with simulated input 1-dB compression point (P1dB) of-12.31 dBm and third order input intercept point (IIP3) of-3.09 dBm. The LNA has a 3-dB bandwidth of 9.3304 GHz, spanning from 55.35 GHz to 64.68 GHz. The power dissipation (PD) and supply voltage (V-DD) of the LNA are 7.34 mW and 1.2 V, respectively.enV-bandLNAtransmission linesRF CMOSmillimetre wave5GGHZjournal-article